Instruction scheduling and software pipelining for modern architectures
نویسندگان
چکیده
منابع مشابه
Modeling Instruction-Level Parallelism for Software Pipelining
Software pipelining is an attractive method to schedule code for processors that exhibit instruction-level parallelism such as pipelined, super-scalar, and (V)LIW machines. It has been implemented for a variety of processors ( e.g. FPS-164[10], Warp[9], Cydra-5[7]), and a number of pipelining algorithms have been described in the literature. Software pipelining produces a schedule so that the e...
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Recently, the microprocessor industry has moved toward multi-core or chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro-architectural limitations. Despite this move, CMPs do not directly improve the performance of single-threaded codes, a characteristic of most applications. In effect, the move to CMPs has shifted even mo...
متن کاملInstruction Scheduling in the Presence of Structural Hazards: An Integer Programming Approach to Software Pipelining
Software pipelining is an eecient instruction scheduling method to exploit the multiple instructions issue capability of modern VLIW architectures. In this paper we develop a precise mathematical formulation based on ILP (Integer Linear Programming) for the software pipelining problem for architectures involving structural hazards. Compared to other heuris-tic methods as well as an ILP-based me...
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Software pipelining is a loop optimization which can optimize loops better, even when all other techniques fail. In this project, Software pipelining is implemented using a scheduling algorithm called window scheduling in SimpleSUIF. Although the algorithm can not be applied to all loops, it is shown that for some loops the software pipelining can improve the performance significantly.
متن کاملSoftware Pipelining and Superblock Scheduling: Compilation Techniques for VLIW Machines
© Copyright Hewlett-Packard Company 1992 Compilers for VLIW and superscalar processors have to expose instruction-level parallelism to effectively utilize the hardware. Software pipelining is a scheduling technique to overlap successive iterations of loops, while superblock scheduling extracts ILP from frequently executed traces. This paper describes an effort to employ both software pipelining...
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ژورنال
عنوان ژورنال: Proceedings of the Institute for System Programming of RAS
سال: 2012
ISSN: 2079-8156,2220-6426
DOI: 10.15514/ispras-2012-22-2